Timed verification of the generic architecture of a memory circuit using parametric timed automata
نویسندگان
چکیده
منابع مشابه
Timed verification of the generic architecture of a memory circuit using parametric timed automata
Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we analyse some crucial timing behaviors of the architecture of SPSMALL memory, a commercial product of STMicroelectronics. Using the model of parametric timed automata and model checker HYTECH, we formally derive a set of linear constraints that ensure the correctness of the response times of the mem...
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Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of some crucial timing behaviours of the architecture of SPSMALL memory. This allows us to check two different implementations of this architecture.
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ژورنال
عنوان ژورنال: Formal Methods in System Design
سال: 2008
ISSN: 0925-9856,1572-8102
DOI: 10.1007/s10703-008-0061-x